In the dynamic landscape of semiconductor design, the quest for efficient system verification tools has reached a pinnacle with IDS-Validate by Agnisys. This robust tool seamlessly integrates with the Portable Stimulus Standard (PSS), offering a streamlined approach to PSS register model generation and revolutionizing the verification process. In this exploration, we delve into the capabilities of IDS-Validate, emphasizing its role in UVM register model generation and exemplifying its impact on the verification workflow.

Efficiency Unleashed: IDS-Validate and PSS Register Model Generation

Agnisys's IDS-Validate proves to be a game-changer in system verification by simplifying the process of PSS register model generation. Leveraging a variety of inputs, including SystemRDL, IP-XACT, IDS-NG, Word, Custom CSV, and more, IDS-Validate empowers users to create a comprehensive PSS register model. This model, enriched with the specifications of registers and sequences, becomes a cornerstone in verifying the functionality of complex systems.

The PSS register model, generated effortlessly through IDS-Validate, encapsulates the rules for accessing registers, providing a clear and concise representation of how the system interacts with programmable registers in the hardware. This streamlining of the register modeling process significantly enhances efficiency in system-level verification.

Bridging the Gap: UVM Register Model Example and Seamless Integration

In the realm of Universal Verification Methodology (UVM), the creation of a robust register model is paramount for thorough verification. IDS-Validate not only simplifies PSS register model generation but also serves as a bridge between the high-level abstractions defined in PSS and the detailed verification processes implemented through UVM.

Consider a scenario where a processor core with control registers needs verification. IDS-Validate facilitates the expression of these registers in a high-level SystemRDL format. Through its seamless integration with PSS, it generates a comprehensive PSS register model, serving as the foundation for UVM sequences. This integration ensures that the verification environment accurately reflects the intended behavior of the design, creating a cohesive workflow for efficient system verification.

Comprehensive Workflow: Firmware and UVM Sequences with IDS-Validate

Beyond PSS register model generation, IDS-Validate propels efficiency by enabling users to generate both firmware and UVM sequences from the same input. Sequences, comprising sets of steps involving the reading or writing of specific bit fields of registers, can be automatically translated into C code for firmware and device driver development. This dual-output capability not only saves time but also enhances flexibility in testing CPUs and embedded systems.

Unifying Sequences with PSS: A Holistic Approach to Verification Challenges

What sets IDS-Validate apart is its holistic approach to sequence generation. By capturing sequences in PSS, Python, spreadsheet format, or GUI (NG), IDS-Validate generates multiple output formats catering to diverse domains:

UVM sequences for verification
System Verilog sequences for validation
C code for firmware and device driver development
Specialized formats for automated test equipment (ATE)
This unified methodology aligns seamlessly with the latest Portable Stimulus Standard (PSS), providing a versatile solution for SOC/IP teams aiming to streamline verification and validation processes across varied domains.

PSS Editor Integration: A User-Friendly Leap Forward

In its latest update, IDS-Validate introduces a dedicated PSS Editor, further enhancing the user experience. This addition empowers engineers to work with PSS files effortlessly, creating and editing portable stimulus models and tests with ease. The PSS Editor features syntax highlighting, code navigation, validation checks, and search-and-replace functionalities, ensuring a user-friendly and efficient workflow.

Conclusion: Elevating System Verification with IDS-Validate

In conclusion, IDS-Validate stands as a catalyst in the realm of semiconductor design verification. By seamlessly integrating with the Portable Stimulus Standard, facilitating PSS register model generation, and offering a comprehensive solution for UVM register model example and sequence generation, IDS-Validate transforms the verification landscape. Its efficiency, versatility, and user-friendly features make it an indispensable tool for SOC/IP teams seeking to elevate the reusability, scalability, and efficiency of their system-level designs.